The field of the present invention relates generally to microdevices and microstructures, and more particularly to microfabrication processes to create micromechanical or microelectromechanical devices with integral electrical isolation structures within the devices.
Microelectromechanical systems (MEMS) refers to a technology in which electrical and mechanical devices are fabricated at substantially microscopic dimensions utilizing techniques well known in the manufacture of integrated circuits. Present commercial applications of MEMS technology are predominantly in pressure and inertial sensing, with an emphasis on automotive applications thereof. For an introduction to the use of MEMS technology for sensors and actuators, see for example the article by Bryzek et al. in IEEE Spectrum, May 1994, pp. 20-31.
The fabrication processes for MEMS, called micromachining, are borrowed from the integrated circuit industry, where semiconductor devices are fabricated using a sequence of patterning, deposition, and etch steps. Surface micromachining has typically used a deposited layer of polysilicon as the structural micromechanical material. The polysilicon is deposited over a sacrificial layer onto a substrate, typically silicon, and when the sacrificial layer is removed the polysilicon remains free standing. Bulk micromachining techniques, rather than using deposited layers on a silicon substrate, etch directly into the silicon wafer to make mechanical structures of the single crystal silicon itself. Bulk micromachining was first practiced using anisotropic wet chemical etchants such as potassium hydroxide, which etch faster in certain crystallographic planes of silicon. However, advancements in reactive ion etching (RIE) technology have made practical, and in many ways preferential, the use of dry plasma etching to define micromechanical structures. Reactive ion etching techniques are independent of crystal orientation, and can create devices exceeding the functionality of surface micromachined devices. The use of single-crystal materials, particularly silicon, can be beneficial for mechanical applications because of the lack of defects and grain boundaries, maintaining excellent structural properties even as the size of the device shrinks.
Deep reactive ion etching techniques developed specifically for the MEMS industry have enabled a greater range of functionality for bulk micromachining. Processes such as those described in U.S. Pat. No. 5,501,893 are now supplied by commercial etch vendors specifically for bulk micromachining. These processes provide silicon etch rates in excess of 2 um/min with vertical profiles and selectivity to photoresist greater than 50:1 or selectivity to silicon oxide greater than 100:1. This enables bulk micromachined structures to span the range from several microns deep to essentially the thickness of an entire wafer (&gt;300 um).
The predominant difficulty in bulk micromachining is the requirement for most devices that the silicon of the microstructure be mechanically connected to but electrically isolated from the substrate silicon. In particular, if the device is electrically activated or transduced, the current path from the structure to the substrate must be reduced or effectively eliminated in order that the device function appropriately. This requirement has proven to be the most difficult to achieve in fabrication.
An example of a process for bulk micromachined structures is described in U.S. Pat. No. 5,719,073 which is assigned to the assignee of the present application, the disclosure of which is hereby incorporated herein by reference. This process uses a single mask layer and appropriate etch and deposition steps to create a fully self-aligned, metalized bulk micromachined structure. Reactive ion etching is used to define and undercut an array of cantilever beams, which are connected together in order to form a more complete functional microstructure. All structure elements and interconnects are formed with the same masking layer, and isotropic dry etch techniques are used to release the structural layer. The advantages of the process are the simplicity of the single masking layer, the reactive ion etch release process, the self-aligned metalization, and high manufacturing yield.
The process flow for the '073 patent defines a pattern in a dielectric mask which is transferred to the single crystal material substrate by a 10-20 um trench etch. After the sidewalls of the trench are protected using a second dielectric layer, such as silicon dioxide, the silicon islands or mesas are undercut and released using an isotropic reactive ion etch. The released silicon mesas essentially become the cantilever beams. A final self-aligned metal layer is deposited onto the oxide layer on the beams, allowing electrical connection to the structure. The process of the '073 patent can be carried out on a wafer having existing integrated circuitry, in which case the individual process steps are all performed at a temperature of less than 300.degree. C.
With the self-aligned metal layer of the '073 patent, only one electrical connection is made to the microstructure. In situations where several connections are necessary, additional photolithography or masking steps must be performed on the released structure. These additional steps limit device yield, since photoresist application on and removal from a released microstructure often results in device failure. Although the metal layer of the '073 patent is self-aligned, it has been found that evaporation or sputtering of metal on the sidewalls of 10-20 um deep beams is a difficult, non-standard process step, and the resulting metal layer is often highly nonuniform in thickness and will coat only a portion of the total beam depth. Further, a metal-oxide-silicon interface is a source of parasitic capacitance for those devices which rely on opposing metal layers for capacitive actuation and transduction and the large area provided by the beam sidewalls in the '073 patent and the metal-oxide-silicon beam structure directly results in a large parasitic capacitance. For many inertial sensing devices, the variable capacitance provided by opposing beam sidewalls is actually exceeded by the parasitic capacitance to the substrate silicon.
An attempt to modify the process of the '073 patent to reduce the level of parasitic capacitance, and thus improve the device performance, resulted in the invention described in U.S. Pat. No. 5,426,070, also assigned to the assignee of the present invention. Here, an oxidation step is carried out to consume sections of the silicon beams, converting these sections completely to oxidized segments. As a result, the remaining silicon of the microstructure is electrically isolated from the substrate silicon by an oxide beam segment. However, the thick oxide layer required for the insulating segment is also grown on sidewall surfaces of the surviving silicon beams, drastically modifying the mechanical performance of the composite beams. In addition, the self-aligned metalization creates only one contact to the microstructure and since the metal is required to coat the sidewalls of the beams, the result is the non-uniform and unreliable metal coverage described above.
Other techniques for providing isolation and parasitic capacitance reduction for bulk micromachined devices have been attempted. Many have relied on the use of specially prepared substrates such as silicon-on-insulator, where the wafer has a built-in buried oxide layer. The microstructure is formed from the silicon layer existing on the top of the buried layer, and released using chemical etching of the buried layer. However, the chemical etch to release the silicon microstructure has relatively low yield, and the substrate itself is specialized and expensive. In Brosnihan, et al., "Embedded interconnect and electrical isolation for high-aspect-ratio, SOI inertial instruments," Transducers 97, pp. 637-640, the authors combine the SOI substrate with nitride and polysilicon isolation blocks. However, the structure definition and release still depend on the buried SOI layer and the resulting expensive substrate preparation.
As bulk micromachined devices increase in complexity it becomes increasingly important to improve their electrical performance. Multiple electrical connections are required for more complex MEMS devices. Electrical isolation between the various connections, and between the structure and the substrate, are also required. Typically such isolation is accomplished in the prior art by separating conducting metal layers by insulating dielectric layers. See for example U.S. Pat. No. 5,611,940. It is also well known in the prior art to provide dielectric isolation regions between microelectronic devices or conductors in integrated circuits, as in U.S. Pat. Nos. 4,688,069 and 4,876,217. A particularly beneficial approach to electrical isolation has been the use of trenches filled with insulating material, described in U.S. Pat. Nos. 4,104,086, 4,509,249, 4,571,819, and 4,519,128. Although the electrical isolation schemes in the prior art are very satisfactory for conventional integrated circuit devices, they have serious shortcomings when applied to microelectromechanical devices.
MEMS devices contain moving mechanical microstructures, typically exhibiting substantially three-dimensional geometries. The existence of these structures precludes, or makes very difficult, the application of electrical isolation schemes such as those described in the prior art. Such schemes involve multiple steps of lithography, etching, and deposition. These steps are not feasible on structures exhibiting large topographic variations, nor on microstructures which have been previously released for motion.
What is required for effective electrical isolation in MEMS devices is a new electrical isolation process which must be compatible with the specific requirements and limitations of MEMS devices, most notably the existence of released, movable microstructures.
What is also required of the electrical isolation process is that it provide isolation between adjacent mechanical structures, between different electrical segments, and between the device and the substrate material. In bulk micromachining, this most often means breaking the electrical continuity between the structure silicon and the substrate silicon. It is desired that such an isolation structure should also provide for reduced parasitic capacitance in the device. MEMS sensors typically require the ability the measure very small changes in electrical charge or capacitance, and therefore must minimize the effect of parasitic circuit elements.
Further what is needed is an electrical isolation process which does not have an adverse impact on the manufacturing yield of MEMS devices. The commercial viability of MEMS technology depends on cost effective manufacturing of products. Prior art electrical isolation schemes may result in very low manufacturing yields and hence unacceptably high costs for most MEMS product applications.